1. Field of the Invention
The present invention relates generally to conversion of analog signals to digital signals, and more particularly to a merged decoding circuit for analog-to-digital flash conversion.
2. Related Art
As the word "flash" implies, flash converters are employed to achieve high speed conversion of analog signals to digital signals. Flash converters yield a conversion of analog-to-digital signals in approximately one clock cycle. There are many ways to perform analog-to-digital conversion, but flash converters are typically the fastest architecture available. To understand how flash converters operate and the problems associated with conventional flash converters, the following example is presented.
FIG. 1 is a high-level block diagram of an example standard flash converter 100. The flash converter 100 consists of two stages: a decoder 102 and a Read Only Memory (ROM) 104. The flash converter 100 generally operates as follows. An analog input signal is received by the decoder 102 via a bus 101. The decoder 102 compares the analog input signal to a reference voltage located within tile circuitry (to be described below) of the decoder 102. The decoder then generates a decoded value representing the voltage level of the analog signal and passes the decoded value to the ROM 104 via a bus 103. The internal architecture of the ROM 104 is comprised of standard ROM circuitry. After receiving the decoded value the ROM 104 generates a digital value associated with the decoded value via a bus 105.
As will become more apparent from the detailed example below, there are many problems associated with standard flash converters, such as a flash converter 100. For instance, the two stage philosophy shown in FIG. 1 requires too much power, too much area on an integrated circuit chip, and is too slow for certain applications.
FIG. 2 is a more detailed example of flash converter 100. FIG. 2 is the same as FIG. 1, but includes a view of the detailed circuitry located within the decoder 102. The decoder 102 includes: a resistor string comprising a plurality of serially connected resistors 202A-202n (where n can be any number); a thermometer 204 comprising a plurality of comparators 206A-206n; and a decode tip 210 comprising a plurality of AND gates 208A-208(n-1) having outputs 209A-209(n-1).
A reference voltage (V.sub.REF) is applied to the top of the resistor string and the bottom of the resistor string is grounded. Alternatively, a positive reference voltage (V.sub.REF+) is applied to the top of the resistor string and a second voltage (V.sub.REF-), less positive than V.sub.REF+, is applied to the bottom of the resistor string 202. Accordingly, a different voltage potential is established between each resistor 202A-202n at a plurality of nodes 205A-205n. Each one of the resistor nodes 205 is coupled to a corresponding comparator 206. The analog input signal is also input to each comparator 206 via the bus 101. In this manner, the analog input signal can be compared with the respective voltages at nodes 205A-205n. The comparators 206A-206n generate an inverted output (207A-207n) and a non-inverted output (207A-207n) based upon the comparison of the input signal 101 with the respective voltage at nodes 205A-205n.
The series of comparators 206 are referred to as the thermometer 204, because they act like a mercury thermometer. In other words, the analog input voltage can range somewhere between the potential of nodes 205A and 205n.
If, for example, the voltage lies between nodes 205D and 205E, then all comparators from comparator 206D and below (e.g., 206C, 206B and 206A) generate a logic 1 at the non-inverting output 207A-D of each respective comparator 206A-D. This indicates that the analog input voltage signal 101 is greater than the respective voltages at nodes 205A-D. At comparator 206E, the input voltage is actually less than the voltage at node 205E. Therefore, all comparators from comparator 206E to 206n will produce a logic 0 at the non-inverted outputs 207E-n of thermometer 204. The outputs 207 of comparators 206 produce what is referred to as the "thermometer code."
The thermometer code via 207 is then decoded by a series of AND gates 208, which comprise the decode tip 210. Each non-inverting output, with the exception of n, is ANDed with the inverting output of the adjacent, next highest thermometer code comparator. AND gate 208A ANDs output A and B, AND gate 208B ANDs output B and C, . . . and AND gate 208(n-1) ANDs output n-1 and n.
If comparators 206A-206D all produce a logic 1 and comparators 206E-n all produce a logic 0 at the non-inverted outputs of the comparators 206, then the outputs are as follows: A, B, C and D are all logic 1 and B, C and D are all logic 0. Accordingly, AND gate 208A produces a logic 0 at output 209A. AND gate 208B produces a logic 0 at output 209B. Similarly, AND gate 208C produces a logic 0 at output 209C.
However, in this example, comparator 206D produces a logic 1 at output D, and comparator 206E produces a logic 0 at non-inverted output E and logic 1 at inverted output E. Therefore, AND gate 208D produces a logic 1 at the output 209D. This is referred to as "decoding the tip" of the thermometer code. Only one output 209A-209(n-1) will be a logic 1.
This output is then fully decoded by the ROM 104 in a conventional manner, that, in this example, generates an appropriate n-bit output on bus 105 after receiving the code via bus 103 (which comprises outputs 209A-209(n-1)). This is the way a standard flash converter 100 operates.
The number of bits output by the flash convertor 100 via the bus 105 determines how many comparators 206 are employed. So for an M-bit converter 100, there are in general, 2.sup.M +1 comparators 206. This allows detection of M bits plus underflow and overflow. In specific applications, where underflow and overflow detection is not required, 2.sup.M -1 comparators are used. As M increases, the number of comparators increases exponentially. Thus, the chip area becomes large and the power requirements increase for the comparators and AND gates. It is, therefore, rare for flash converters 100 to exceed more than eight-bits at the bus 105. In addition, the multi-step conversion process described above has several levels of gate delays. Accordingly, the multi-stage conversion process is time consuming, costly in terms of area on the chip and consumes too much power for the required process involved.
Therefore, what is needed is a flash converter that: (1) is able to operate faster than current flash converters (e.g., less gate delays and latency); (2) requires less power than current flash converters; and (3) requires less area on a chip.